UPSD3312D datasheet(214/272 Pages) STMICROELECTRONICS

214 / 272 page

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PSD module

UPSD33xx

214/272

Doc ID 9685 Rev 7

Figure 71.

Using the Design Assistant in PSDsoft Express for simple PLD example

27.4.39

Latched address output mode

In the MCU module, the data bus Bits D0-D15 are multiplexed with the low address Bits A0-

A15, and the ALE signal is used to separate them with respect to time. Sometimes it is

necessary to send de-multiplexed address signals to external peripherals or memory

devices. Latched Address Output mode will drive individual demuxed address signals on

pins of Ports A or B. Port pins can be designated for this function on a pin-by-pin basis,

meaning that an entire port will not be sacrificed if only a few address signals are needed.

To activate this mode, the desired pins on Port A or Port B are designated as “Latched

Address Out” in PSDsoft. Then in the 8032 initialization firmware, a logic ’1’ is written to the

csiop Control register for Port A or Port B in each bit position that corresponds to the pin of

the port driving an address signal. Table 144 and Table 145 define the csiop Control register

locations and bit assignments.

The latched low address byte A4-A7 is available on both Port A and Port B. The high

address byte A8-A15 is available on Port B only. Selection of high or low address byte is

specified in PSDsoft Express.

Table 144.

Latched Address output, Port A Control register (address = csiop+offset 02h)(1)(2)(3)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7

(addr A7)

PA6

(addr A6)

PA5

(addr A5)

PA4

(addr A4)

PA3

(addr A3)

PA2

(Addr A2)

PA1

(addr A1)

PA0

(addr A0)

Port A not available on 52-pin UPSD33xx devices

For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O

Default state for register is 00h after reset or power-up

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