M30622ECTFP datasheet(146/184 Pages) MITSUBISHI

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146

Tentative Specifications REV.A

Mitsubishi microcomputers

M16C / 62T Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Specifications in this manual are tentative and subject to change.

Under

development

A-D Converter

Item

Performance

Method of A-D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (Note 1) 0V to AVCC (VCC)

Operating clock

φAD (Note 2) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) (VCC = 5V)

Resolution

8-bit or 10-bit (selectable)

Absolute precision

q8-bit resolution

±2LSB

q10-bit resolution

±3LSB

When the extended analog input pins ANEX0, ANEX1, AN00 to AN07,

and AN20 to AN27 are used as the external operation amp connection mode:

±7LSB

Operating modes

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

Analog input pins

8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 16 pins (AN00 to AN07,

AN20 to AN27)

(Note 3)

A-D conversion start condition • Software trigger

A-D conversion starts when the A-D conversion start flag changes to “1”

• External trigger (can be retriggered)

A-D conversion starts when the A-D conversion start flag is “1” and the

___________

ADTRG/P97 input changes from “H” to “L”

Conversion speed per pin • Without sample and hold function

8-bit resolution: 49

φAD cycles, 10-bit resolution: 59 φAD cycles

• With sample and hold function

8-bit resolution: 28

φAD cycles, 10-bit resolution: 33 φAD cycles

A-D Converter

The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling

amplifier. Pins P100 to P107, P95, P96, P00 to P07, and P20 to P27 also function as the analog signal input pins. The

direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at

address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input

pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from

VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of

03D716 to connect VREF.

The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low

8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low

8 bits are stored in the even addresses.

Table 1.20.1 shows the performance of the A-D converter. Figure 1.20.1 shows the block diagram of the

A-D converter, and Figures 1.20.2 and 1.20.3 show the A-D converter-related registers.

Note 1: Does not depend on use of sample and hold function.

Note 2: Divide the frequency if f(XIN) exceeds 10MHZ, and make

φAD frequency equal to 10MHZ.

Without sample and hold function, set the

φAD frequency to 250kHZ min.

With the sample and hold function, set the

φAD frequency to 1MHZ min.

Note 3: The pins are not used as the analog input pins can be used as normal I/O ports, or I/O pins of

each peripheral function.

Table 1.20.1. Performance of A-D converter

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