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M30622ECTFP bảng dữ liệu(PDF) 26 Page - Mitsubishi Electric Semiconductor |
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M30622ECTFP bảng dữ liệu(HTML) 26 Page - Mitsubishi Electric Semiconductor |
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26 / 184 page ![]() 26 Tentative Specifications REV.A Mitsubishi microcomputers M16C / 62T Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Specifications in this manual are tentative and subject to change. Under development Memory Space Expansion Functions The data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). The bank selection bits are used to set a bank number for accessing data lying between 4000016 and BFFFF16. Assigning 1 to the offset bit provides the means to set offsets covering 4000016. Figure 1.8.5 shows the memory location and chip select areas in expansion mode 2. _______ The area relevant to CS0 ranges from 4000016 through FFFFF16. As for the area from 4000016 through _______ BFFFF16, the bank number set by use of the bank selection bits are output from the output terminals CS3 _______ _______ _______ - CS1 only in accessing data. In fetching a program, bank 7 (1112) is output from CS3 - CS1. As for the _______ _______ area from C000016 through FFFFF16, bank 7 (1112) is output from CS3 - CS1 without regard to accessing data or to fetching a program. _______ _______ _______ In accessing an area irrelevant to CS0, a chip select signal CS3 (400016 - 7FFF16), CS2 (800016 - _______ 27FFF16), and CS1 (2800016 - 3FFFF16) is output depending on the address as in the past. Figure 1.8.6 shows an example of connecting the MCU with a 4-M byte ROM and to a 128-K byte SRAM. _______ _______ _______ _______ Connect the chip select of 4-M byte ROM with CS0. Connect M16C’s CS3, CS2, and CS1 with address inputs A21, A20, and A19 respectively. Connect M16C’s output A19 with address input A18. Figure 1.8.7 shows the relationship between addresses of the 4-M byte ROM and those of M16C. An example of connecting the MCU with external memories in expansion mode 2 (M30622MC, Microprocessor mode) 17 8 D0 to D7 A0 to A16 A17 RD WR CS1 CS2 CS3 CS0 A19 D0 to D7 A0 to A16 A17 A18 A19 OE CS DQ0 to DQ7 A0 to A16 S2 W OE S1 A20 A21 Note 1. If only one chip select terminal (S1 or S2) is present, decoding by use of an external circuit is required. Note 2. M30623(80-pin package) is not provided with the output pin for the chip select signal. Note 3. The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. With no offsets effected, banks switch from one 512-K byte segment to another 512-K byte segment. Bank selection bits need to be changed in dealing with data lying across the boundary between banks every time a bank switches to another. Assigning 1 to the offset bit brings about offsets covering 4000016 so that data can be accessed without changing the bank selection bits. For instance, accessing 8000016 of bank 0 with offsets ef- fected causes the output bank number to turn to 1, and AD19 is inverted to be out- put; this results in accessing 4000016 of bank 1. On the other hand, the SRAM’s chip select assumes _______ that CS0=1 (not selected) _______ and CS2=0 (selected), so _______ connect CS0 with S2 and _______ ____ CS2 with S1. If the SRAM doesn’t have a bipolar chip select input terminal, decode _______ _______ CS0 and CS2 externally. Figure 1.8.6. An example of connecting the MCU with external memories in expansion mode 2 |
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