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AN4570 bảng dữ liệu(PDF) 34 Page - STMicroelectronics |
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AN4570 bảng dữ liệu(HTML) 34 Page - STMicroelectronics |
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34 / 46 page ![]() Interfacing with an 8-bit NAND Flash memory AN4570 34/46 DocID026804 Rev 1 Based on the NAND Flash memory access timings shown in Figure 10, the following equations are found: • The write or read access time is the time between the falling edge and the rising edge of the NAND Flash memory Chip Select signal. It is computed as a function of the FMC timing parameter: ((SET + 1) + (WAIT + 1) + (HOLD + 1)) × tHCLK ≥ Write/Read access • The Wait time is measured between the falling edge and the rising edge of the Write/Read Enable signal: Write/Read Enable signal low to high = (WAIT + 1) × tHCLK • For write access, the HIZ parameter is the time measured between the falling edge of the Chip Select signal and the data setup on bus: (HIZ+1) x tHCLK ≥ Chip Select setup time to Data setup. • The HOLD timing is given in the NAND datasheet as follows: (HOLD +1) x tHCLK = Write Enable High to Chip Enable / Address/Command Latch High To make sure of the correct timing configuration of the FMC, the timings have to take into consideration: • The maximum read/write access time • The different internal FMC delays • The different internal memory delays Hence, we have the following equations following the NAND512W3A NAND datasheet: • (SET + 1) x tHCLK ≥ max (tCS, tCLS, tALS, tCLR, tAR) - tWP • (WAIT + 1) x tHCLK ≥ max (tWP, tRP) • (HIZ + 1) x tHCLK ≥ max (tCS, tALS, tCLS) + (tWP - tDS) • (HOLD + 1) x tHCLK ≥ max (tCH, tCLH, tALH) • ((WAIT + 1) + (HOLD + 1) + (SET + 1)) x tHCLK ≥ max (tWC/RC) Considering the different timings in the FMC and the memory, the equations become: • WAIT must verify: (WAIT + 1)× tHCLK ≥ (tREA + tsu(D-NOE)) WAIT ≥ (tREA + tsu(D-NOE)) /tHCLK - 1 Note: tsu(D-NOE) is specified in the STM32F30xxD/E datasheets. tsu(D-NOE) = 25 ns Table 8 gives the meanings and values of the NAND512W3A2C memory parameters. Table 8. NAND512W3A2C Flash memory timings Symbol Parameter Value Unit tCEA Chip Enable low to output valid 35 ns tWP Write Enable low to Write Enable high 15 ns |
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