AN4570 datasheet(11/46 Pages) STMICROELECTRONICS

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AN4570

Interfacing with a non-multiplexed, asynchronous 16-bit NOR Flash memory

In this application note, the M29W128FL memory is used as a reference. The M29W128FL

memory is a 16-bit, asynchronous, non-multiplexed NOR Flash memory. Based on these

data, the FMC is configured as follows:

Bank 2 is selected to support the NOR Flash memory device:

•

Bank 2 is enabled: BCR2_MBKEN bit set to ‘1’

•

Memory type is NOR: BCR2_MTYP is set to ‘10’ to select the NOR memory type

•

Data bus width is 16-bit: BCR2_MWID is set to ‘01’ to select the 16-bit width

•

It is a non-multiplexed memory: BCR2_MUXEN is reset.

All remaining parameters must be kept cleared.

2.2

Timing computation

As described above, for asynchronous NOR Flash-like memories, there are different

possible access protocols. The first step is therefore to define the kind of protocol that

should be used with the specific memory. The choice depends on the different control

signals and the behavior of the memory during read and write transactions.

In the case of an asynchronous NOR Flash memory, the Mode2 protocol will be used. If the

used memory can provide an NADV signal, the Extended Mode B protocol should be used.

With the M29W128FL, we will use the Mode2 protocol. We will therefore not use any

extended mode and the timings will be the same for read and write operations. In this case,

the NOR memory controller needs two timing parameters: ADDSET and DATAST.

These parameters are computed according to the NOR Flash memory characteristics and

according to the HCLK clock of the STM32F30xxD/E.

Based on the NOR Flash memory access timings illustrated in Figure 3 and Figure 4, the

following equations are found:

•

The write or read access time is the time between the falling edge and the rising edge

of the memory Chip Select signal. This time is computed as a function of the FMC

timing parameter:

((ADDSET + 1) + (DATAST + 1)) × tHCLK

≥ Write access time

•

In write operations, the DATAST parameter is measured between the falling edge and

the rising edge of the write signal as follows:

tWP = DATAST × tHCLK

≥ Write Enable signal low to high

To have a correct configuration of the FMC timings, the timings have to take into account:

•

the maximum read/write access time

•

the different internal FMC delays

•

the different internal memory delays

Hence, we have:

((ADDSET + 1) + (DATAST + 1)) × tHCLK = max (tWC)

DATAST × HCLK = tWP

For read access, DATAST must verify:

DATAST

≥ (tAVQV + tsu(Data_NE) + tv(A_NE))/tHCLK – ADDSET – 4

Table 4 gives the meanings and values of the NOR Flash memory parameters.

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