UM0851 datasheet(230/245 Pages) STMICROELECTRONICS

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Power management section

UM0851

230/245

Doc ID 16604 Rev 2

Middle level clock management layer

The middle management clock layer acts as a transition between the lower layer which

actually interacts with the hardware and the kernel.

The drivers calling into the kernel for the clock requirements need to ensure that if the clock

source is shared between multiple drivers, clk_enable() calls must be balanced by the same

number of clk_disable() calls for the clock source to be disabled. Each clk_enable() call

increments the reference count of the clock and its dependencies as described in

Section 10.2.2

above.

The Middle Management layer tracks the reference counts and resolves the dependencies

in the clock dependency tree.

Lower level clock management layer

The lower level clock management layer actually interacts with the hardware to ensure that

the proper settings are being done in the respective registers required for the proper

functioning of the clock tree.

At the time when the kernel is being booted, the clock tree initialization takes place based

upon a static clock tree that has been defined in (arc/arm/mach-

spearxxx/include/arm/spearxxx_clock.h). This tree provides in the exhaustive clock

dependencies that have been maintained for the SPEAr system.

Note:

The clocks in the RAS hardware area are not covered in the software management of the

clocks as yet.

One of the most important data structures that has been used in the clock framework is the

struct clk.

struct clk {

struct res_handle

*res;

struct list_head

node;

struct list_head

clk_got;

struct list_head

clk_enabled;

struct module

*owner;

const char

*name;

int

id;

struct clk

*parent;

unsigned long

rate;

__u32

flags;

volatile u32

*enable_reg;

__u8

enable_bit;

__s8

usecount;

void

(*recalc)(struct clk *);

int

(*set_rate)(struct clk *, unsigned long);

long

(*round_rate)(struct clk *, unsigned long);

void

(*init)(struct clk *);

int

(*enable)(struct clk *);

void

(*disable)(struct clk *);

__u32

prcmid;

fixed_div;

volatile u32*clksel_reg;

u32

clksel_mask;

const struct clksel*clksel;

const struct dpll_data*dpll_data;

__u8

rate_offset;

__u8

src_offset;

};

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