UM0851 datasheet(59/245 Pages) STMICROELECTRONICS

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UM0851

Communication device drivers

Doc ID 16604 Rev 2

59/245

/* this function will register the mdio bus basic operation and scan all PHYs in this

bus */

mdiobus_register(&bp->mii_bus);

/* after this function, if there's a valid PHY at address “addr”,

“bp->mii_bus.phy_map[phy_addr]” will point to a phy_device structure,

otherwise it is NULL */

Through platform_device/driver, the MACB drivers will get the phy_device structure and the

MAC base register address from the top layer. The following code is in MACB driver

drivers/net/arm/spear_macb.c

/* to start the PHY */

phy_start(bp->phy_dev);

/* in the run time, the network environment may change. So the state of PHY

(link on/off, 100M/10M) may also change. At the same time, it is necessary

to change the MAC setting in software. This can be done through a callback

function "macb_handle_link_change */

phydev = phy_connect(bp->dev, bp->phy_dev->dev.bus_id, &macb_handle_link_change, 0);

General kernel interface

Please refer to the corresponding chapter of the GMAC section (GMAC interface to kernel)

4.2.4

Socket buffer management

Please refer to the corresponding chapter of the GMAC section (Section 4.1.4: Concept of

socket buffers).

4.2.5

Cache coherency

Working with the CPU cache results in increased performance, but introduces

cache/memory coherence problems as external DMAs can only access the external

memory.

There are two cache strategies in the MACB driver.

●

FIFO descriptor memory is allocated as an uncached memory block. It uses the void*

dma_alloc_coherent(struct device*, size_t, dma_addr_t*, gfp_t) function to allocate the

uncached memory, which uses the pgprot_noncached macro to set the page table.

Since there is never a cached copy of this buffer, CPU access is slower but there are no

such coherency problems.

●

The real data buffer whose address is stored in the FIFO descriptor is allocated as a

cached memory block. The driver allocates the RX buffers directly using kmalloc(),

while the TX buffers are allocated by network stack upper layers. In both cases the skb-

>data field is populated with a data buffer pointer. Since these RX/TX buffers are

cached, the driver must explicitly guarantee the coherence between memory and

cache. For this purpose, the Linux kernel provides the function dma_addr_t

dma_map_single(struct device *dev, void *ptr, size_t size,enum dma_data_direction

dir). The last parameter may be set to DMA_FROM_DEVICE or DMA_TO_DEVICE

according to whether the cache must be invalidated (to read incoming data) or flushed

(to send outcoming data). The dma_unmap_single() routine is not present in Linux for

ARM.

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