UM0851 datasheet(56/245 Pages) STMICROELECTRONICS

56 / 245 page

Communication device drivers

UM0851

56/245

Doc ID 16604 Rev 2

Figure 11.

MACB diagram

The statistics register block contains registers for counting various types of event associated

with transmit and receive operations. These registers, along with the status words stored in

the receive buffer list, enable software to generate network management statistics

compatible with IEEE 802.3 Clause 30.

The control registers drive the MDIO interface, setup up DMA activity, start frame

transmission and select modes of operation such as full or half duplex. The register interface

is compatible with the AMBA APB bus standard.

The receive block checks for valid preamble, FCS, alignment and length, and presents

received frames to the address checking block and DMA interface

The transmit block takes data from the DMA interface, adds preamble and, if necessary, pad

and FCS, and transmits data according to the CSMA/CD (carrier sense multiple access with

collision detect) protocol. The start of transmission is deferred if CRS (carrier sense) is

active. If COL (collision) becomes active during transmission, a jam sequence is asserted

and the transmission is retried after a random back off. CRS and COL have no effect in full

duplex mode.

The DMA block connects to external memory through its AMBA AHB or ASB bus interface. It

contains receive and transmit FIFOs for buffering frame data. It loads the transmit FIFO and

empties the receive FIFO using AHB or ASB bus master operations. Receive data is not

sent to memory until the address checking logic has determined that the frame should be

copied.

Receive or transmit frames are stored in one or more buffers. Receive buffers have a fixed

length of 128 bytes. Transmit buffers range in length between 0 and 2047 bytes, and up to

128 buffers are permitted per frame. The DMA block manages transmit and receive frame-

buffer queues. These queues can hold multiple frames.

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