UM0851 datasheet(118/245 Pages) STMICROELECTRONICS

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Communication device drivers

UM0851

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Doc ID 16604 Rev 2

Physical port parameters

●

has_tsa

True for TDM/E1 port, false for RS485 port.

●

ts0_delay

Only for TDM/E1 port, delay between SYNC signal and beginning of TS0.

●

cts_enable

Only for RS485 port, enable collision detection or not. Initial value is set by kernel

configuration.

●

cts_delay

Only for RS485 port, set delay when controller start to sample the CTS signal. This

parameter tells the controller when to sample the CTS signal after transmitting one bit.

The delay can be calculated by (cts_delay+2)/freq_ahb. Be sure NOT to set delay more

than one clock cycle.

●

penalty

Only for RS485 port, set waiting time before re-transmitting the frame when collision

occurs. Refer to the SPEAR310 User Manual for more details.

●

tx_falling_edge

Tx edge config. True for transmit at falling clock edge, false for transmit at rising clock

edge.

●

rx_rising_edge

Rx edge config. True for sample at rising clock edge, false for sample at falling clock

edge.

Logical channel parameters

●

common_flag

Enables common flag feature. Refer to the SPEAR310 User Manual for more details..

●

crc32_enable

True for CRC32, false for CRC16. Default is CRC16.

●

flag_enable

Transmits flag when idle. Refer to the SPEAR310 User Manual for more details..

●

addr_recog

Address recognition mode. Refer to the SPEAR310 User Manual for more details..

Parameters are defined in the global data array spear_hdlc_port[].

4.10.5

Assigning timeslots for TDM/E1 interface

SPEAr HDLC driver uses two Ioctls to assign timeslots for the TDM/E1 interface:

●

SIOCDEVASSIGNSLOT

Only for the TDM/E1 port, assign Tx/Rx timeslot for logical HDLC channel.

●

SIOCDEVREMOVESLOT

Only for the TDM/E1 port, remove Tx/Rx timeslot for logical HDLC channel.

Code sample:

struct ifreq req;

unsigned int data[2];

sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP);

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