UM0434 datasheet(110/390 Pages) STMICROELECTRONICS

110 / 390 page

UM0434

Instruction model

111/391

Note:

Accesses that cross a translation boundary may be restarted. A misaligned access that

crosses a page boundary is restarted in its entirety in the event of a TLB miss of the second

portion of the access. This may result in the first portion being accessed twice.

Accesses that cross a translation boundary where endianness changes cause a byte-

ordering data storage interrupt.

5.7

Memory synchronization and reservation instructions

Table 103 lists the e200z3 implementation details for the memory synchronization and load

and store with reservation instructions.

5.8

Branch prediction

The e200z3 instruction fetching mechanism uses a branch target buffer (BTB), which holds

branch target addresses combined with a 2-bit saturating up-down counter scheme for

branch prediction. These bits can take four values: strongly taken, weakly taken, weakly not

taken, and strongly not taken. This mechanism is described in

Chapter 8.3.5: Change-of-

Flow instruction pipeline operation on page 213.”

Branch paths are predicted by a BTB and subsequently checked to see if the prediction was

correct. This enables operation beyond a conditional branch without waiting for the branch to

Table 103.

Memory synchronization and reservation instructions e200z3 specific details

Instruction

e200z3 implementation

msync

Provides synchronization and memory barrier functions. msync completes only after all preceding

instructions and data memory accesses complete. Subsequent instructions in the stream are not

dispatched until after the msync ensures these functions have been performed.

mbar

Behaves identically to msync; the mbar MO field is ignored by the e200z3 core.

lwarx/

stwcx.

Implemented as described in the

EREF. If the EA for either instruction is not a multiple of four, an

alignment interrupt is invoked. The e200z3 allows lwarx and stwcx. to access a page marked as

write-through required without invoking a data storage interrupt.

As Book E allows, the e200z3 does not require the EAs for a stwcx. and the preceding lwarx to be to

the same reservation granule.

Reservation granularity is implementation dependent. The e200z3 does not define a reservation

granule explicitly; it is defined by external logic. When no external logic is provided, the e200z3 does

not compare addresses; thus, the effective implementation granularity is null.

The e200z3 implements an internal status flag, HID1[ATS], which is set when an lwarx completes

without error. It remains set until it is cleared by one of the following:

–An stwcx. executes without error

– The e200z3 core

p_rsrv_clr input is asserted. See Chapter 9.”

– The reservation is invalidated when an external interrupt is signaled and HID0[ICR] is set.

The e200z3 treats lwarx and stwcx. as cache-inhibited and guarded, regardless of page attributes.

The e200z3 core input

p_xfail_b is sampled at termination of an stwcx. store transfer to allow an

external agent or mechanism to indicate that the stwcx. failed to update memory, even though a

reservation existed for the store when it was issued. This is not considered an error and causes the

condition codes for the stwcx. to be written as if it had no reservation. Also, any outstanding

reservation is cleared.

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