UM0434 datasheet(89/390 Pages) STMICROELECTRONICS

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UM0434

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4.16.3

TLB configuration registers (TLB

nCFG)

The TLB

nCFG read-only registers provide information about each specific TLB that is

visible to the programming model.

TLB configuration register 0 (TLB0CFG)

TLB0CFG, shown in

Table 69, provides information about the configuration of TLB0.

Because the e200z3 MMU design does not implement TLB0, this register reads as all zeros.

It is supplied to allow software to query it in a way compatible with other Book E designs.

The TLB0CFG fields are described in

Table 70.

Table 68.

MMUCFG field descriptions

Bits

Name

Description

32–48

—

Reserved, should be cleared.

49–52

NPIDS

Number of PID registers.

0001 This version of the MMU implements one PID register (PID0).

53–57

PIDSIZE

PID register size.

00111 PID registers contain 8 bits in this version of the MMU.

58–59

—

Reserved, should be cleared.

60–61

NTLBS

Number of TLBs.

01 This version of the MMU implements two TLB structures: a null TLB0 and a

populated TLB1.

62–63

MAVN

MMU architecture version number.

00 This version of the MMU implements version 1.0 of the Book E MMU architecture.

Table 69.

TLB configuration register 0 (TLB0CFG)

50 51

Field

ASSOC

MINSIZE

MAXSIZE

IPROT

AVAIL

—

NENTRY

Reset

All zeros (TLB0 is not implemented)

R/W

Read only

SPR

SPR 688

Table 70.

TLB0CFG field descriptions

Bits

Name

Description

32–39

ASSOC

Associativity.

40–43

MINSIZE

Minimum page size.

44–47

MAXSIZE

Maximum page size.

IPROT

Invalidate protect capability.

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