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IVPR fields are defined in

Table 29.

Interrupt vector offset registers (IVORs)

IVORs, shown in

Table 30, hold the quad-word index from the base address provided by the

IVPR for each interrupt type.

The IVOR fields are defined in

Table 31.

SPR numbers corresponding to IVOR16–IVOR31 are reserved. IVOR32–IVOR47 and

IVOR60–IVOR63 are reserved. SPR numbers for IVOR32–IVOR63 are allocated for

implementation-dependent use (IVOR32–IVOR34 (SPR 528–530) are defined by the EIS).

IVOR assignments are shown in

Table 32.

Table 28.

Interrupt vector prefix register (IVPR)

Field

Vector Base

—

Reset

Undefined on

m_por assertion, unchanged on p_reset_b assertion

R/W

SPR

SPR 63

Table 29.

IVPR field descriptions

Bits

Name

Description

32–47

Vector

Base

Defines the base location of the vector table, aligned to a 64-Kbyte boundary.

Provides the high-order 16 bits of the location of all interrupt handlers. IVPR ||

IVOR

n values are concatenated to form the address of the handler in memory.

48–63

—

Reserved, should be cleared.

Table 30.

Interrupt vector offset registers (IVOR)

47 48

59 60 61

Field

—

Vector offset

—

Reset

Undefined on

m_por assertion, unchanged on p_reset_b assertion

R/W

SPR

(See

Table 24.)

Table 31.

IVOR field descriptions

Bits

Name

Setting description

32–47

—

Reserved, should be cleared.

48–59

Vector

offset

Provides a quad-word index from the base address provided by the IVPR to

locate an interrupt handler.

—

Reserved, should be cleared.

61–63

Context selector (e200z3-specific). When multiple hardware contexts are

supported, this field is used to select an operating context for the interrupt

handler. This value is loaded into the CURCTX field of the context control register

(CTXCR) as part of the interrupt vectoring process. When multiple hardware

contexts are not supported, CS is not implemented and is read as zero.

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