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–

TLB configuration registers (TLB0CFG and TLB1CFG). Read-only registers

that allow software to query the configuration of the TLBs.

–

System version register (SVR). A read-only register that identifies the version

(model) and revision level of the system that includes an e200z3 processor.

Note:

Although other processors may implement similar or identical registers, it is not guaranteed

that the implementation of e200z3-core-specific registers is consistent among PowerPC

processors.

All e200z3 SPR definitions comply with the Book E definitions.

4.3

e200z3-Specific Device Control Registers

In addition to the SPRs, implementations may also implement one or more device control

registers (DCRs). The e200z3 core implements a set of device control registers to perform a

parallel signature in the parallel signature unit (PSU). These registers may not be supported

by other PowerPC processors. For details, see

Chapter 4.19: Parallel signature unit

registers on page 103.”

4.4

Processor control registers

This section discusses machine state, processor ID, processor version, and system version

registers.

4.4.1

Machine state register (MSR)

The MSR, shown in

Figure 6, defines the state of the processor. Chapter 6: Interrupts and

exceptions,” describes how the MSR is affected by interrupts.

Table 6.

Machine state register (MSR)

MSR fields are described in

Table 7.

Field

—

UCLESPE

—

WE CE — EE PR FP ME FE0 — DE FE1

—

IS DS

—

Reset

All zeros

R/W

Table 7.

MSR field descriptions

Bits

Name

Description

32–36

—

Reserved, should be cleared.

UCLE

User cache lock enable.

0 Execution of the cache locking instructions is disabled in user mode

(MSR[PR] = 1).

Instead, the data storage interrupt is taken, and ILK or DLK is set in the ESR.

1 Execution of the cache lock instructions is enabled in user mode.

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