UM0434 datasheet(74/390 Pages) STMICROELECTRONICS

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UM0434

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40–41 IAC12M

Instruction address compare 1/2 mode.

00 Exact address compare. IAC1 debug events can occur only if the address of the instruction

fetch is equal to the value specified in IAC1. IAC2 debug events can occur only if the address of

the instruction fetch is equal to the value specified in IAC2.

01 Address bit match. IAC1 debug events can occur only if the address of the instruction fetch

ANDed with the contents of IAC2 is equal to the contents of IAC1, also ANDed with the contents

of IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are used.

10 Inclusive address range compare. IAC1 debug events can occur only if the address of the

instruction fetch is greater than or equal to the value specified in IAC1 and less than the value

specified in IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are used.

11 Exclusive address range compare. IAC1 debug events can occur only if the address of the

instruction fetch is less than the value specified in IAC1 or is greater than or equal to the value

specified in IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are used.

42–47

—

Reserved

48–49 IAC3US

Instruction address compare 3 user/supervisor mode.

00 AC3 debug events are not affected by MSR[PR].

01 Reserved.

10 AC3 debug events can occur only if MSR[PR] = 0 (supervisor mode).

11 AC3 debug events can occur only if MSR[PR] = 1 (user mode).

50–51 IAC3ER

Instruction address compare 3 effective/real mode.

00 AC3 debug events are based on effective address.

01 Unimplemented in the e200z3 (Book E real address compare), no match can occur.

10 AC3 debug events are based on effective address and can occur only if MSR[IS] = 0.

11 AC3 debug events are based on effective address and can occur only if MSR[IS] = 1.

52–53 IAC4US

Instruction address compare 4 user/supervisor mode.

00 AC4 debug events are not affected by MSR[PR].

01 Reserved.

10 IAC4 debug events can occur only if MSR[PR] = 0 (supervisor mode).

11 IAC4 debug events can occur only if MSR[PR] = 1 (user mode).

54–55 IAC4ER

Instruction address compare 4effective/real mode.

00 AC4 debug events are based on effective address.

01 Unimplemented in the e200z3 (Book E real address compare), no match can occur.

10 IAC4 debug events are based on effective address and can occur only if MSR[IS] = 0.

11 IAC4 debug events are based on effective address and can occur only if MSR[IS] = 1.

Table 53.

DBCR1 field descriptions (continued)

Bits

Name

Description

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