UM0434 datasheet(109/390 Pages) STMICROELECTRONICS

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Instruction model

UM0434

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5.5

BookE instruction extensions

The variable length encoding (VLE) provides an extension to 32-bit PowerPC Book E. There

are additional operations defined using an alternate instruction encoding to enable reduced

code footprint. This alternate encoding set is selected on an instruction page basis. A single

page attribute bit selects between standard PowerPC Book E instruction encodings and

VLE instructions for that page of memory. This page attribute is an extension to the

PowerPC Book E page attributes. Pages can be freely intermixed, allowing for a mixture of

code using both types of encodings.

Instruction encodings in pages marked as using the VLE extension are either 16 or 32 bits

long, and are aligned on 16-bit boundaries. Therefore, all instruction pages marked as VLE

are required to use big-endian byte ordering.

This section describes the various extensions to Book E instructions to support the VLE

extension.

rfci, rfdi, rfi—no longer mask bit 62 of CSRR0, DSRR0, or SRR0 respectively. The

destination address is [D,C]SRR0[32:62] || 0b0.

bclr, bclrl, bcctr, bcctrl—no longer mask bit 62 of the LR or CTR respectively. The

destination address is [LR,CTR][32:62] || 0b0.

5.6

Memory access alignment support

The e200z3 core provides hardware support for unaligned memory accesses. However,

there is a performance degradation for accesses that cross a 64-bit (8 byte) boundary. For

these cases, the throughput of the load/store unit is degraded to one misaligned load every

2 cycles. Stores misaligned across a 64-bit (8 byte) boundary can be translated at a rate of

2 cycles per store. Frequent use of unaligned memory accesses is discouraged because of

the impact on performance.

Table 102.

Implementation-Specific instruction summary

Mnemonic

Implementation details

mfapidi

Unimplemented instructions

mfdcrx, mtdcrx

stwcx.

Address match with prior lwarx not required for store to be performed

mfdcr, mtdcr(1)

The e200z3 CPU takes an illegal instruction interrupt for unsupported DCR values

Optionally supported instructions

tlbivax

tlbre

tlbsx

tlbsync

tlbwe

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