IO13PDB0V0 datasheet(195/197 Pages) MICROSEMI

195 / 197 page

SmartFusion Customizable System-on-Chip (cSoC)

Re vi s i on 12

6 - 13

Revision 0

(continued)

"SmartFusion Development Tools" section was replaced with new content.

3-1

The pin description tables were revised by adding additional pins to reflect the pinout

for A2F500.

5-1

through

5-16

The descriptions for "GNDSDD1" and "VCC33SDD1" were revised.

5-1, 5-2

The description for "VCC33A" was revised.

5-2

The pin tables for the "FG256" and "FG484" were replaced with tables that compare

pin functions across densities for each package.

5-42

Draft B

(December 2009)

The "Digital I/Os" section was renamed to the "I/Os and Operating Voltage" section

and information was added regarding digital and analog VCC.

The "SmartFusion cSoC Family Product Table" and "Package I/Os: MSS + FPGA

I/Os" section were revised.

The terminology for the analog blocks was changed to "programmable analog,"

consisting of two blocks: the analog front-end and analog compute engine. This is

reflected throughout the text and in the "SmartFusion cSoC Block Diagram".

The "Product Ordering Codes" table was revised to add G as an ordering code for

eNVM size.

Timing tables were populated with information that has become available for speed

grade –1.

N/A

All occurrences of the VMV parameter were removed.

N/A

The SDD[n] voltage parameter was removed from Table 2-2 • Analog Maximum

Ratings.

2-2

Table 36-4 • Flash Programming Limits – Retention, Storage and Operating

Temperature was replaced with Table 2-4 • FPGA and Embedded Flash

Programming, Storage and Operating Limits.

2-4

The "Thermal Characteristics" section was revised extensively.

2-7

Table 2-8 • Power Supplies Configuration was revised significantly.

2-10

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in

SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static

Power Consumption in SmartFusion cSoCs were updated.

2-12

Figure 2-2 • Timing Model was updated.

2-19

The temperature associated with the reliability for LVTTL/LVCMOS in Table 2-34 • I/O

Input Rise Time, Fall Time, and Related I/O Reliability was changed from 110º to

100º.

2-29

The values in Table 2-78 • Combinatorial Cell Propagation Delays were updated.

2-57

Table 2-85 • Electrical Characteristics of the Low Power Oscillator is new. Table 2-84 •

Electrical Characteristics of the Main Crystal Oscillator was revised.

2-62

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,

VCC = 1.425 V and Table 2-91 • FlashROM Access Time, Worse Commercial Case

Conditions: TJ = 85°C, VCC = 1.425 V are new.

2-75

The performance tables in the "Programmable Analog Specifications" section were

revised, including new data available. Table 2-98 • Analog Sigma-Delta DAC is new.

2-77

The "256-Pin FBGA" table for A2F200 is new.

4-15

Revision

Changes

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