IO13PDB0V0 datasheet(54/197 Pages) MICROSEMI

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SmartFusion DC and Switching Characteristics

2- 42

R e v i sio n 1 2

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. SoC Products Group LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require

series terminations for better signal quality and to control voltage swing. Termination is also required at

both ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using SoC Products Group LVDS macros can achieve up to 200 MHz with a maximum

of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available

in the LVDS section in Table 2-65.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case commercial operating conditions, at the farthest receiver: RS =60 Ω

and RT =70 Ω, given Z0 =50 Ω (2") and Zstub =50 Ω (~1.5").

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

BIBUF_LVDS

Receiver

Transceiver

Receiver

Transceiver

Driver

RS RS

Zstub

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation

187 W

100



Z0 = 50 

100



100



–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA

Bourns Part Number: CAT16-PC4F12

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