IO13PDB0V0 datasheet(31/197 Pages) MICROSEMI

31 / 197 page

SmartFusion Customizable System-on-Chip (cSoC)

Re vi s i on 12

2 - 19

User I/O Characteristics

Timing Model

Figure 2-2 •

Timing Model

Operating Conditions: –1 Speed, Commercial Temperature Range (TJ = 85°C),

Worst Case VCC = 1.425 V

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL (applicable to

FPGA /O bank, EMC pin)

LVPECL

(Applicable

to FPGA

I/O Bank,

EMC pin)

LVDS,

BLVDS,

M-LVDS

(Applicable for

FPGA I/O Bank,

EMC pin)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTLOutput drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 VOutput drive strength = 4 mA

High slew rate

LVTTLOutput drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

tPD = 0.57 ns

tPD = 0.49 ns

tDP = 1.53 ns

tPD = 0.89 ns

tDP = 2.81 ns (FPGA I/O Bank, EMC pin)

tPD = 0.51 ns

tDP = 3.87 ns (FPGA I/O Bank, EMC pin)

tPD = 0.48 ns

tDP = 4.13 ns (FPGA I/O Bank, EMC pin)

tPD = 0.48 ns

tPY = 0.81 ns

(FPGA I/O Bank, EMC pin)

tCLKQ = 0.56 ns

tOCLKQ = 0.60 ns

tSUD = 0.44 ns

tOSUD = 0.32 ns

tDP = 2.81 ns

(FPGA I/O Bank, EMC pin)

tPY = 0.81 ns (FPGA I/O Bank, EMC pin)

tPY = 1.55 ns

tCLKQ = 0.56 ns

tSUD = 0.44 ns

tPY = 0.81 ns

(FPGA I/O Bank, EMC pin)

tICLKQ = 0.24 ns

tISUD = 0.27 ns

tPY = 1.46 ns

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