IO13PDB0V0 datasheet(190/197 Pages) MICROSEMI

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Datasheet Information

6- 8

R ev isio n 1 2

Revision 6

(continued)

Dynamic power values were updated in the following tables. The table subtitles

changed where FPGA I/O banks were involved to note "I/O assigned to EMC I/O pins"

(SAR 30987).

Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software

Settings

Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software

Settings.

2-10

2-11

The "Timing Model" was updated (SAR 30986).

2-19

Values in the timing tables for the following sections were updated. Table subtitles

were updated for FPGA I/O banks to note "I/O assigned to EMC I/O pins" (SAR

30986).

"Overview of I/O Performance" section: Table 2-24, Table 2-25

"Detailed I/O DC Characteristics" section: Table 2-38, Table 2-39, Table 2-40,

Table 2-44, Table 2-45, Table 2-46, Table 2-50, Table 2-51, Table 2-52, Table 2-56,

Table 2-57, Table 2-58, Table 2-61, Table 2-62

"LVDS" section: Table 2-65

"LVPECL" section: Table 2-68

"Global Tree Timing Characteristics" section: Table 2-80, Table 2-81

2-23

2-26

2-40

2-42

2-59

The "PQ208" section and pin tables are new (SAR 31005).

5-34

Global clocks were removed from the A2F060 pin table for the "CS288" and "FG256"

packages, resulting in changed function names for affected pins (SAR 31033).

5-43

Revision 5

(December 2010)

Table 2-2 • Analog Maximum Ratings was revised. The recommended CM[n] pad

voltage (relative to ground) was changed from –11 to –0.3 (SAR 28219).

2-2

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays was revised

to change the values for 100ºC.

2-9

Power-down and Sleep modes, and all associated notes, were removed from

Table 2-8 • Power Supplies Configuration (SAR 29479). IDC3 and IDC4 were

renamed to IDC1 and IDC2 (SAR 29478). These modes are no longer supported. A

note was added to the table stating that current monitors and temperature monitors

should not be used when Power-down and/or Sleep mode are required by the

application.

2-10

The "Power-Down and Sleep Mode Implementation" section was deleted (SAR

29479).

N/A

Values for PAC9 and PAC10 for LVDS and LVPECL were revised in Table 2-10 •

Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings and

Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software

Settings*.

2-10,

2-11

Values for PAC1 through PAC4, PDC1, and PDC2 were added for A2F500 in

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in

SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static

Power Consumption in SmartFusion cSoCs

2-12,

2-13

The equation for "Total Dynamic Power Consumption—PDYN" in "SoC Mode" was

revised to add PMSS. The "Microcontroller Subsystem Dynamic Contribution—PMSS"

section is new (SAR 29462).

2-14,

2-18

Information in Table 2-24 • Summary of I/O Timing Characteristics—Software Default

Settings (applicable to FPGA I/O banks) and Table 2-25 • Summary of I/O Timing

Characteristics—Software Default Settings (applicable to MSS I/O banks) was

updated.

2-25

Revision

Changes

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