S25FS256S datasheet(20/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

The WP# function is not available when the Quad Mode is enabled (CR1V[1]=1). The WP# function is

replaced by IO2 for input and output during Quad Mode for receiving addresses, and data to be programmed

(values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK,

in SDR commands, and on every edge of SCK, in DDR commands).

WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the

host system if not used for Quad Mode or protection.

3.8

IO3 / RESET#

IO3 is used for input and output during Quad Mode (CR1V[1]=1) for receiving addresses, and data to be

programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling

edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

The IO3 / RESET# signal may also be used to initiate the hardware reset function when the reset feature is

enabled by writing Configuration Register 2 non-volatile bit 5 (CR2V[5]=1). The input is only treated as

RESET# when the device is not in Quad-I/O mode, CR1V[1] = 0, or when CS# is high. When Quad I/O mode

is in use, CR1V[1]=1, and the device is selected with CS# low, the IO3 / RESET# is used only as IO3 for

information transfer. When CS# is high, the IO3 / RESET# is not in use for information transfer and is used as

the RESET# input. By conditioning the reset operation on CS# high during Quad Mode, the reset function

remains available during Quad Mode.

When the system enters a reset condition, the CS# signal must be driven high as part of the reset process

and the IO3 / RESET# signal is driven low. When CS# goes high the IO3 / RESET# input transitions from

being IO3 to being the RESET# input. The reset condition is then detected when CS# remains high and the

IO3 / RESET# signal remains low for tRP. If a reset is not intended, the system is required to actively drive

IO3 / Reset# to high along with CS# being driven high at the end of a transfer of data to the memory.

Following transfers of data to the host system, the memory will drive IO3 high during tCS. This will ensure that

IO3 / Reset is not left floating or being pulled slowly to high by the internal or an external passive pull-up.

Thus, an unintended reset is not triggered by the IO3 / RESET# not being recognized as high before the end

of tRP.

The IO3 / RESET# signal is unused when the reset feature is disabled (CR2V[5]=0).

The IO3 / RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if

not used for Quad Mode or the reset function. The internal pull-up will hold IO3 / RESET high after the host

system has actively driven the signal high and then stops driving the signal.

Note that IO3 / RESET# cannot be shared by more than one SPI-MIO memory if any of them are operating in

Quad I/O mode as IO3 being driven to or from one selected memory may look like a reset signal to a second

non-selected memory sharing the same IO3 / RESET# signal.

3.9

Voltage Supply (VDD)

VDD is the voltage source for all device internal logic. It is the single voltage used for all device internal

functions including read, program, and erase.

3.10

Supply and Signal Ground (VSS)

VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output

drivers.

3.11

Not Connected (NC)

No device internal signal is connected to the package connector nor is there any future plan to use the

connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit

Board (PCB).

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