S25FS256S datasheet(12/154 Pages) SPANSION

12 / 154 page

S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

Overview

2.1

General Description

The Spansion S25FS-S family devices are flash non-volatile memory products using:

 MirrorBit technology - that stores two data bits in each memory array transistor

 Eclipse architecture - that dramatically improves program and erase performance

 65 nm process lithography

TheS25FS-S family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single

bit serial input and output (Single I/O or SIO) is supported as well as optional 2-bit (Dual I/O or DIO) and 4-bit

wide Quad I/O (QIO) or Quad Peripheral Interface (QPI) serial commands. This multiple width interface is

called SPI Multi-I/O or MIO. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI

that transfer address and read data on both edges of the clock.

The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be

programmed in one operation, resulting in faster effective programming and erase than prior generation SPI

program or erase algorithms.

Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS-S family

devices at the higher clock rates supported, with Quad or DDR Quad commands, the instruction read transfer

rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing

signal count dramatically.

The S25FS-S family products offer high densities coupled with the flexibility and fast performance required by

a variety of mobile or embedded applications. They are an excellent solution for systems with limited space,

signal connections, and power. They are ideal for code shadowing to RAM, executing code directly (XIP), and

storing reprogrammable data.

S25FS256S bảng dữ liệu(PDF) 12 Page - SPANSION