S25FS256S datasheet(84/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

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(Pre limin ar y)

 The exact password must be entered in order for the unlocking function to occur. If the password unlock

command provided password does not match the hidden internal password, the unlock operation fails in

the same manner as a programming operation on a protected sector. The P_ERR bit is set to 1, the WIP bit

remains set, and the PPB Lock bit remains cleared to 0.

 The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This

makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit

combinations in an attempt to correctly match a password. The Read Status Register 1 command may be

used to read the WIP bit to determine when the device has completed the password unlock command or is

ready to accept a new password command. When a valid password is provided the password unlock

command does not insert the 100 µs delay before returning the WIP bit to 0.

 If the password is lost after selecting the Password mode, there is no way to set the PPB Lock bit.

9.5

Recommended Protection Process

During system manufacture, the flash device configuration should be defined by:

1. Programming the OTP configuration bits in CR1NV[5, 3:2], CR2NV, CR3NV, and CR4NV as

desired.

2. Program the Secure Silicon Region (OTP area) as desired.

3. Program the PPB bits as desired via the PPBP command.

4. Program the Non-Volatile Data Learning Pattern (NVDLR) if it will be used in DDR read

commands.

5. Program the Password register (PASS) if password protection will be used.

6. Program the ASP Register as desired, including the selection of the persistent or password ASP

protection mode in ASPR[2:1]. It is very important to explicitly select a protection mode so that later

accidental or malicious programming of the ASP register and OTP configuration is prevented. This

is to ensure that only the intended OTP protection and configuration features are enabled.

During system power-up and boot code execution:

1. Trusted boot code can determine whether there is any need to program additional SSR (OTP area)

information. If no SSR changes are needed the FREEZE bit (CR1V[0]) can be set to 1 to protect

the SSR from changes during the remainder of normal system operation while power remains on.

2. If the Persistent Protection mode is in use, trusted boot code can determine whether there is any

need to modify the persistent (PPB) sector protection via the PPBP or PPBE commands. If no PPB

changes are needed the PPBLOCK bit can be cleared to 0 via the PPBL to protect the PPB bits

from changes during the remainder of normal system operation while power remains on.

3. The Dynamic (DYB) Sector Protection bits can be written as desired via the DYBAR.

S25FS256S bảng dữ liệu(PDF) 84 Page - SPANSION