S25FS256S datasheet(28/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

4.3

Interface States

This section describes the input and output signal levels as related to the SPI interface behavior.

Legend

= No driver - floating signal

= Host driving VIL

= Host driving VIH

= Either HL or HH

= HL or HH or Z

= Toggling between HL and HH

= Memory driving VIL

= Memory driving VIH

= Either ML or MH

4.3.1

Power-Off

When the core supply voltage is at or below the VDD (Low) voltage, the device is considered to be powered off.

The device does not react to external signals, and is prevented from performing any program or erase

operation.

4.3.2

Low-Power Hardware Data Protection

When VDD is less than VDD (Cut-off) the memory device will ignore commands to ensure that program and

erase operations can not start when the core supply voltage is out of the operating range.

Table 4.1 Interface States Summary

Interface State

VDD

SCK

CS#

IO3 /

RESET#

WP# / IO2

SO / IO1

SI / IO0

Power-Off

<VDD (low)

Low-Power Hardware Data Protection

<VDD (cut-off)

Power-On (Cold) Reset

≥V

DD (min)

Hardware (Warm) Reset Non-Quad Mode

≥V

DD (min)

Hardware (Warm) Reset Quad Mode

≥V

DD (min)

Interface Standby

≥V

DD (min)

Instruction Cycle (Legacy SPI)

≥V

DD (min)

Single Input Cycle

Host to Memory Transfer

≥V

DD (min)

Single Latency (Dummy) Cycle

≥V

DD (min)

Single Output Cycle

Memory to Host Transfer

≥V

DD (min)

Dual Input Cycle

Host to Memory Transfer

≥V

DD (min)

Dual Latency (Dummy) Cycle

≥V

DD (min)

Dual Output Cycle

Memory to Host Transfer

≥V

DD (min)

Quad Input Cycle

Host to Memory Transfer

≥V

DD (min)

Quad Latency (Dummy) Cycle

≥V

DD (min)

XXXX

Quad Output Cycle

Memory to Host Transfer

≥V

DD (min)

DDR Quad Input Cycle

Host to Memory Transfer

≥V

DD (min)

DDR Latency (Dummy) Cycle

≥V

DD (min)

MV or Z

DDR Quad Output Cycle

Memory to Host Transfer

≥V

DD (min)

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