S25FS256S datasheet(32/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

4.5

Data Protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the

hardware design. These are described below. Other software managed protection methods are discussed in

the software section of this document.

4.5.1

Power-Up

When the core supply voltage is at or below the VDD (Low) voltage, the device is considered to be powered off.

The device does not react to external signals, and is prevented from performing any program or erase

operation. Program and erase operations continue to be prevented during the Power-On Reset (POR)

because no command is accepted until the exit from POR to the Interface Standby state.

4.5.2

Low Power

When VDD is less than VDD (Cut-off) the memory device will ignore commands to ensure that program and

erase operations can not start when the core supply voltage is out of the operating range.

4.5.3

Clock Pulse Count

The device verifies that all non-volatile memory and register data modifying commands consist of a clock

pulse count that is a multiple of eight bit transfers (byte boundary) before executing them. A command not

ending on an 8-bit (byte) boundary is ignored and no error status is set for the command.

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