S25FS256S datasheet(29/154 Pages) SPANSION

29 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

4.3.3

Power-On (Cold) Reset

When the core voltage supply remains at or below the VDD (Low) voltage for ≥ tPD time, then rises to ≥ VDD

(Minimum) the device will begin its Power-On Reset (POR) process. POR continues until the end of tPU. During

tPU the device does not react to external input signals nor drive any outputs. Following the end of tPU the

device transitions to the Interface Standby state and can accept commands. For additional information on

POR see Power-On (Cold) Reset on page 38

4.3.4

Hardware (Warm) Reset

A configuration option is provided to allow IO3 to be used as a hardware reset input when the device is not in

Quad Mode or when it is in Quad Mode and CS# is high. When IO3 / RESET# is driven low for tRP time the

device starts the hardware reset process. The process continues for tRPH time. Following the end of both tRPH

and the reset hold time following the rise of RESET# (tRH) the device transitions to the Interface Standby state

and can accept commands. For additional information on hardware reset see Reset on page 38

4.3.5

Interface Standby

When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface

waits for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes low

to begin a new command.

While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is

in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the

algorithm when the entire device returns to standby current draw.

4.3.6

Instruction Cycle (Legacy SPI Mode)

When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device

captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the

device captures the next lower significance bit of the 8-bit instruction. The host keeps CS# low, and drives the

Write Protect (WP#) and IO3/RESET signals as needed for the instruction. However, WP# is only relevant

during instruction cycles of a WRR or WRAR command and is otherwise ignored. IO3/RESET# is driven high

when the device is not in Quad Mode (CR1V[1]=0) or QPI Mode (CR2V[6]=0) and hardware reset is not

required.

Each instruction selects the address space that is operated on and the transfer format used during the

remainder of the command. The transfer format may be Single, Dual I/O, Quad I/O, or DDR Quad I/O. The

expected next interface state depends on the instruction received.

Some commands are stand alone, needing no address or data transfer to or from the memory. The host

returns CS# high after the rising edge of SCK for the eighth bit of the instruction in such commands. The next

interface state in this case is Interface Standby.

4.3.7

Instruction Cycle (QPI Mode)

In QPI Mode, when CR2V[6]=1, instructions are transferred 4 bits per cycle. In this mode, instruction cycles

are the same as a Quad Input Cycle. See Quad Input Cycle - Host to Memory Transfer on page 30.

4.3.8

Single Input Cycle - Host to Memory Transfer

Several commands transfer information after the instruction on the single Serial Input (SI) signal from host to

the memory device. The host keeps RESET# high, CS# low, and drives SI as needed for the command. The

memory does not drive the Serial Output (SO) signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or

data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly

to Single, Dual, or Quad Output Cycle states.

S25FS256S bảng dữ liệu(PDF) 29 Page - SPANSION

S25FS256S bảng dữ liệu(HTML) 29 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL