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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AMC7812SPAP bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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AMC7812SPAP bảng dữ liệu(HTML) 10 Page - Texas Instruments |
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10 / 92 page  t HD, STA t SU, DAT t HD, DAT t SU, STA t SU, STO t HD,STA t LOW t HIGH t R t F t BUF SDA SCL S Sr P S S=STARTCondition Sr=RepeatedSTARTCondition P=STOPCondition =ResistorPull-Up AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com I 2C-COMPATIBLE TIMING DIAGRAMS Figure 1. Timing for Standard and Fast Mode Devices on the I2C Bus TIMING CHARACTERISTICS: SDA and SCL for Standard and Fast Modes (1) At –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AGND = DGND = 0V, and IOVDD = 2.7V to 5.5V, unless otherwise noted. STANDARD FAST MODE MODE PARAMETER MIN MAX MIN MAX UNIT fSCL (2) SCL clock frequency 0 100 0 400 kHz tLOW Low period of the SCL clock 4.7 — 1.3 — µs tHIGH High period of the SCL clock 4.0 — 0.6 — µs tSU, STA Set-up time for a repeated start condition 4.7 — 0.6 — µs Hold time (repeated) start condition. After this tHD, STA 4.0 — 0.6 — µs period, the first clock pulse is generated tSU, DAT Data set-up time 250 — 100 — ns tHD, DAT Data hold time: for I2C-bus devices 0 3.45 0 0.9 µs tSU, STO Set-up time for stop condition 4.0 — 0.6 — µs tR Rise time of both SDA and SCL signals — 1000 20 + 0.1CB (3) 300 ns tF Fall time of both SDA and SCL signals — 300 20 + 0.1CB (3) 300 ns tBUF Bus free time between a stop and start condition 4.7 — 1.3 — µs CB Capacitive load for each bus line — 400 — 400 pF tSP Pulse width of spike suppressed NA NA 0 50 ns (1) All values refer to VIHmin and VILmax levels. (2) An SCL operating frequency of at least 1kHz is recommended to avoid activating the I2C timeout function. See the Timeout Function section for details. (3) CB = total capacitance of one bus line in pF. 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: AMC7812 |
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