IMX53IEC datasheet(73/173 Pages) FREESCALE

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Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

4.7.4.2

eMMC4.4 (Dual Data Rate) eSDHCv3 AC Timing

Figure 37 depicts the timing of eMMC4.4. Table 50 lists the eMMC4.4 timing characteristics. Be aware

that only DATA is sampled on both edges of the clock (not applicable to CMD).

Figure 37. eMMC4.4 Timing

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD7

eSDHC Input Setup Time

tISU

2.5

—

SD8

eSDHC Input Hold Time4

tIH

2.5

—

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0

–50 MHz.

3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0

–52 MHz.

4To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 50. eMMC4.4 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (MMC Full Speed/High Speed)

fPP

052

MHz

eSDHC Output / Card Inputs CMD, DAT (Reference to CLK)

SD2

eSDHC Output Delay

tOD

-4.5

4.5

Table 49. SD/eMMC4.3 Interface Timing Specification (continued)

Parameter

Symbols

Min

Max

Unit

SD1

SD2

SD3

output from eSDHCv3 to card

DAT1

......

DAT7

DAT0

input from card to eSDHCv3

DAT1

......

DAT7

DAT0

SCK

SD4

SD2

......

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