IMX53IEC datasheet(67/173 Pages) FREESCALE

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Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

4.7.2.3

ECSPI Master Mode Timing

Figure 32 depicts the timing of ECSPI in master mode. Table 46 lists the ECSPI master mode timing

characteristics.

4.7.2.4

ECSPI Slave Mode Timing

Figure 33 depicts the timing of ECSPI in slave mode. Table 47 lists the ECSPI slave mode timing

characteristics.

Table 46. ECSPI Master Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1

SCLK Cycle Time—Read

SCLK Cycle Time—Write

tclk

—ns

CS2

SCLK High or Low Time—Read

SCLK High or Low Time—Write

tSW

—ns

CS3

SCLK Rise or Fall1

1 See specific I/O AC parameters Section 4.5, “I/O AC Parameters”

tRISE/FALL

——

CS4

SSx pulse width

tCSLH

Half SCLK period

—

CS5

SSx Lead Time (CS setup time)

tSCS

5—

CS6

SSx Lag Time (CS hold time)

tHCS

5—

CS7

MOSI Propagation Delay (CLOAD =20pF)

tPDmosi

-0.5

2.5

CS8

MISO Setup Time

tSmiso

8.5

—

CS9

MISO Hold Time

tHmiso

0—

CS10

RDY to SSx Time2

2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

tSDRY

5—

Table 47. ECSPI Slave Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1

SCLK Cycle Time–Read

SCLK Cycle Time–Write

tclk

—ns

CS2

SCLK High or Low Time–Read

SCLK High or Low Time–Write

tSW

—ns

CS4

SSx pulse width

tCSLH

Half SCLK period

—

CS5

SSx Lead Time (CS setup time)

tSCS

5—

CS6

SSx Lag Time (CS hold time)

tHCS

5—

CS7

MOSI Setup Time

tSmosi

4—

CS8

MOSI Hold Time

tHmosi

4—

CS9

MISO Propagation Delay (CLOAD =20pF)

tPDmiso

417

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