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WM8961GEFL/V bảng dữ liệu(PDF) 27 Page - Wolfson Microelectronics plc

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WM8961GEFL/V bảng dữ liệu(HTML) 27 Page - Wolfson Microelectronics plc

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WM8961
Pre-Production
w
PP, August 2009, Rev 3.1
27
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4 (04h)
Clocking1
8:6
ADCDIV[2:0]
000
Defines the ADC 256fs clock, which is further
divided by 2.
000 : 256fs = SYSCLK / 1.0 (default
=12.288MHz, fs= 48 KHz)
001 : Reserved
010 : 256fs = SYSCLK / 2
011 : 256fs = SYSCLK / 3
100 : 256fs = SYSCLK / 4
101 : 256fs = SYSCLK / 5.5
110 : 256fs = SYSCLK / 6
111 : Reserved
The polarity of the output signal can be changed under software control using the ADCPOL[1:0]
register bits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
ADC and DAC
Control 1
6:5
ADCPOL[1:0]
00
ADC Data invert
00 : Both Channels normal polarity
01 : Left Channel Inverted
10 : Right Channel Inverted
11 : Both Channels Inverted
Table 10 ADC Polarity Select
ADC DIGITAL VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to
+17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for
a given eight-bit code X is given by:
0.375
× (X-192) dB for 1 ≤ X ≤ 239;
MUTE for X = 0
+17.625dB for 239
≤ X ≤ 255
The ADCVU bit controls the loading of digital volume control data. When ADCVU is set to 0, the
LADCVOL or RADCVOL control data will be loaded into the respective control register, but will not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to ADCVU. This makes it possible to update the gain of both channels simultaneously.



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