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WM8961GEFL/V bảng dữ liệu(PDF) 62 Page - Wolfson Microelectronics plc

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Giải thích chi tiết về linh kiện  Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
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WM8961
Pre-Production
w
PP, August 2009, Rev 3.1
62
Figure 37 DSP Mode Audio Interface (mode B, LRP=0, Slave)
DIGITAL AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised in
Table 44. MS selects audio interface operation in master or slave mode. In Master mode BCLK and
LRC are outputs. The frequency of LRC is set by LRCLK_RATE and BCLK is set by the bits BCLKDIV
(See “Clocking and Sample Rates”). In Slave mode BCLK and LRC are inputs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
Digital Audio
Interface
Format
8
ALRSWAP
0
Left/Right ADC channel swap
1 = Swap left and right ADC data in
audio interface
0 = Output left and right data as normal
7
BCLKINV
0
BCLK invert bit (for master and slave
modes)
0 = BCLK not inverted
1 = BCLK inverted
6
MS
0
Master / Slave Mode Control
0 = Enable slave mode
1 = Enable master mode
5
DLRSWAP
0
Left/Right DAC Channel Swap
0 = Output left and right data as normal
1 = Swap left and right DAC data in
audio interface
4
LRP
0
Right, left and I
2S modes – LRC polarity
0 = normal LRC polarity
1 = invert LRC polarity
DSP Mode – mode A/B select
0 = MSB is available on 2
nd BCLK rising
edge after LRC rising edge (mode A)
1 = MSB is available on 1
st BCLK rising
edge after LRC rising edge (mode B)
3:2
WL[1:0]
10
Audio Data Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
1:0
FORMAT[1:0]
10
Audio Data Format Select
00 = Right justified
01 = Left justified
10 = I
2S Format
11 = DSP Mode
Table 44 Audio Data Format Control



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