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WM8961
Pre-Production
w
PP, August 2009, Rev 3.1
21
Figure 8 2-Wire Serial Control Interface (single write)
RW
Device ID
Sr
A
P
MSByte Data
(1)
LSByte Data
A
Device ID
S
A
Index
(0)
A
RW
A
Figure 9 2-Wire Serial Control Interface (single read)
Figure 10 2-Wire Serial Control Interface (multiple write using auto-increment)
Figure 11 2-Wire Serial Control Interface (multiple read using auto-increment)
A Write Sequencer allows register write sequences to be stored in an area of memory on the WM8961
and then triggered by another register write. This allows complex sequences of updates to the
WM8961 registers without the constant intervention of the processor. To use the write sequencer, an
MCLK must be present and CLK_SYS_ENA=1. Refer to section headed “Control Write Sequencer”
for operation of the Write Sequencer.
ALERT RESPONSES
By default WM8961 does not respond to Control interface alert response messages. This can be
enabled by setting the ARA_ENA bit as detailed in Table 3.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R252 (FCh)
General test 1
1
ARA_ENA
0
Alert Response Address Enable
0 : off
1 : on
0
AUTO_INC
1
Enable Auto-Increment
0 : off
1 : on
Table 3 Control Interface Settings



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