WM8961GEFLSLASHV datasheet(75/116 Pages) WOLFSON

75 / 116 page

WM8961

Pre-Production

PP, August 2009, Rev 3.1

EXAMPLE SAMPLE RATE CONFIGURATIONS

Using the registers shown in Table 51, some example ADCDIV and DACDIV settings have been

calculated and detailed in Table 52 for various sample rates and SYSCLKs.

ADC /

DAC

SAMPLE

RATE

(kHz)

RECOMMENDED

SYSCLK

(MHZ)

DACDIV

ADCDIV

12.288

100 => DAC clk = 12.288 MHz/4.0 = 3.072MHz (=64fs)

000 => 256fs = 12.288 MHz/1.0 =12.288 MHz

8.192

100 => DAC clk = 8.192 MHz/4.0 = 2.048MHz (=64fs)

000 => 256fs = 8.192 MHz/1.0 = 8.192 MHz

6.144

010 => DAC clk = 6.144 MHz/2.0 = 3.072MHz (=128fs)

000 => 256fs = 6.144 MHz/ 1.0 = 6.144 MHz

3.072

000 => DAC clk = 3.072 MHz/1.0 = 3.072MHz (=256fs)

000 => 256fs = 3.072 MHz/ 1.0 = 3.072 MHz

44.1

11.2896

100 => DAC clk = 11.2896MHz/4.0 = 2.8224MHz (=64fs)

000 => 256fs = 11.2896MHz/1.0 =11.2896MHz

22.05

5.6448

010 => DAC clk = 5.6448 MHz/2.0 = 2.8224MHz (=128fs)

000 => 256fs = 5.6448 MHz/1.0 =5.6448 MHz

3.072

000 => DAC clk = 3.072 MHz/1.0 = 3.072MHz (=384fs)

000 => 256fs = 3.072 MHz/ 1.0 = 3.072 MHz

Table 55 ADC and DAC Recommended DACDIV and ADCDIV Configuration

If only the DAC is being used (ADC not used) then the SYSCLK can be reduced to save power. This

is shown in Table 56.

DAC SAMPLE RATE (kHz)

RECOMMENDED SYSCLK

(MHZ)

DACDIV

3.072

000 => DAC clk = 3.072 MHz /1.0 = 3.072 MHz

(=64fs)

2.048

000 => DAC clk = 2.048 MHz/1.0 = 2.048 MHz

(=64fs)

3.072

000 => DAC clk = 3.072 MHz/1.0 = 3.072 MHz

(=128fs)

3.072

000 => DAC clk = 3.072 MHz/1.0 = 3.072 MHz

(=256fs)

44.1

2.8224

000 => DAC clk = 2.8224 MHz/1.0 = 2.8224

MHz (=64fs)

22.05

2.8224

000 => DAC clk = 2.8224 MHz/1.0 =

2.8224MHz (=128fs)

3.072

000 => DAC clk = 3.072 MHz/1.0 = 3.072MHz

(=384fs)

Table 56 Recommended DACDIV Configuration for DAC Playback Only

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