WM8961GEFLSLASHV datasheet(41/116 Pages) WOLFSON

41 / 116 page

WM8961

Pre-Production

PP, August 2009, Rev 3.1

ADCL_DAC_SVOL or

ADCR_DAC_SVOL

SIDETONE

VOLUME

0000

-36

0001

-33

0010

-30

0011

-27

0100

-24

0101

-21

0110

-18

0111

-15

1000

-12

1001

-9

1010

-6

1011

-3

1100

1101

1110

1111

Table 26 Digital Sidetone Volume in dB

DAC OVERSAMPLING

In order to increase the signal to noise ratio (SNR) of the DAC output, the DAC_OSR128 register bit

can be used to increase the oversampling rate of the DAC as shown in Table 31. The

MANUAL_MODE register bit is detailed in “ADC and DAC Clocking and Sample Rates”. There will be

a slight increase in power consumption when 128OSR mode is selected.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

ADC & DAC

Control 2

DAC_OSR128

DAC 128 Over Sampling Rate

0: 64x DAC oversampling

1: If MANUAL_MODE=0, automatically

configure DACDIV[2:0] for 128OSR

mode. This will give a SNR

improvement at the expense of power

Table 27 DAC Oversampling Control

ANALOGUE OUTPUTS

WM8961 has 2 analogue output paths. One path drives a ground referenced headphone output which

is powered by a charge pump. In this path, a DC servo is used to remove any offsets from the

headphone outputs. The second path drives the Class D speaker outputs.

HEADPHONE OUTPUTS

The headphone output consists of 2 stages, a Volume PGA, followed by an output drive stage

containing an integrated PGA, as illustrated in Figure 18. The headphone output stage must be

enabled during normal operation, which permits power saving when not in use. The headphone bias

current can be controlled to improve SNR. For details of the DC Servo, refer to the “DC Servo”

section.

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