WM8961GEFLSLASHV datasheet(17/116 Pages) WOLFSON

tên linh kiện	WM8961GEFL/V

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

INTERNAL POWER ON RESET CIRCUIT

Figure 5 Internal Power-on Reset Circuit Schematic

The WM8961 includes an internal Power-On-Reset Circuit, as shown in Figure 5, which is used to

reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and

monitors DVDD. It asserts PORB low if AVDD or DVDD is below a minimum threshold.

DVDD

AVDD

Vpord_on

DGND

AGND

Internal POR active

Device Ready

Internal

POR active

No Power

POR

Undefined

Vpora_off

Vpora

INTERNAL PORB

Figure 6 Typical Power up Sequence when AVDD is Applied before DVDD

Figure 6 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above

the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted

low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now

AVDD is at full supply level. Next DVDD rises to Vpord_on and PORB is released high and all registers

are in their default state and writes to the control interface may take place.

On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the

minimum threshold Vpora_off.

WM8961GEFL/V bảng dữ liệu(PDF) 17 Page - Wolfson Microelectronics plc