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WM8961GEFL/V bảng dữ liệu(PDF) 25 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V bảng dữ liệu(HTML) 25 Page - Wolfson Microelectronics plc |
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25 / 116 page  WM8961 Pre-Production w PP, August 2009, Rev 3.1 25 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R32 (20h) ADCL signal path 5:4 LMICBOOST [1:0] 00 Left Channel Input PGA Boost Gain 00 = +0dB 01 = +13dB 10 = +20dB 11 = +29dB R33 (21h) ADCR signal path 5:4 RMICBOOST [1:0] 00 Right Channel Input PGA Boost Gain 00 = +0dB 01 = +13dB 10 = +20dB 11 = +29dB Table 7 Microphone PGA Boost Control The output of the boost stage drives the ADC. MICROPHONE INPUT CONNECTION EXAMPLE AND MICROPHONE BIASING The input PGAs can be configured to use a single-ended input microphone. In the single ended microphone input configuration the microphone signal can be input to LINPUT. An example of this is shown in Figure 13 which also shows the microphone biasing. Figure 13 Single Ended Microphone Configuration Example MICROPHONE BIASING CIRCUIT The MICBIAS output pin provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBSEL register bit. When MBSEL=0, MICBIAS=5/6 ×AVDD and when MBSEL=1, MICBIAS=7/6 ×AVDD. The output can be enabled or disabled using the MICB control bit. (Note that MBSEL=1 only allowed if MICVDD is greater than +2.40V) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R25 (19h) Power management (1) 1 MICB 0 Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON R48 (30h) Additional Control (4) 0 MBSEL 1 Microphone Bias Voltage Control 1 = 7/6 * AVDD 0 = 5/6 * AVDD Table 8 Microphone Bias Control |
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