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TLK3114SCZPV bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TLK3114SCZPV bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 68 page ![]() 1−2 XAUI 4 PCS TLK3114SC TX+ TX− RX+ RX− TDA..D[9:0] TCA..D RCA..D RDA..D[9:0] 4 4 4 CWDM Optics MAC/ Packet Processor TLK3114SC or TLK3104SA 4 4 4 4 XGMII Line Card Figure 1−2. System Block Diagram (PCS Implementation) Figure 1−3 shows an example system block diagram for the TLK3114SC device used to provide the system backplane interconnect. MAC/ Packet Processor XGMII XAUI 4 TLK3114SC TX+ TX− RX+ RX− TDA..D[9:0] TCA..D RCA..D 4 4 4 RDA..D[9:0] Framer/ PCS PHY/ Optics Switch Fabric XGMII XAUI 4 TLK3114SC TX+ TX− RX+ RX− TDA..D[9:0] TCA..D RCA..D 4 4 4 RDA..D[9:0] System Backplane Line Card Figure 1−3. System Block Diagram (Backplane Interconnect Implementation) The TLK3114SC device supports the IEEE 802.3 defined management data input/output (MDIO) interface to allow ease in configuration and status monitoring of the link. The TLK3114SC device supports the IEEE 1149.1 defined JTAG test port for ease in board manufacturing test. It also supports a comprehensive series of built-in tests for self-test purposes including internal serial loopback and pseudorandom bit stream (PRBS) generation and verification. |
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