TLK3114SCZPV datasheet(47/68 Pages) TI1

47 / 68 page

3−29

Table 3−22. Channel D Configuration Registers Bit Definitions (Register 20)

BIT(S)

NAME

DESCRIPTION

READ/WRITE

15:12

Reserved

Read returns all 0s, writes are ignored.

Read-only

Clock tolerance compensation

1 = Enable clock tolerance compensation.

0 = Disable clock tolerance compensation (default).

Logically ORed with register 16, bit 11

Read/Write

10:9

Multifunction pin output

Multifunction (MFD) pin configuration for channel D.

Bit 10

Bit 9

MFD Output

HSTL = 1, SSTL_2 = 0 (default)

1 = Comma detected, 0 = data

Logically ORed with register 16, bits 10 and 9.

Read/Write

Loss of signal detection

1 = Enable LOS condition described in Table 3−7 for channel D (default).

0 = Disable this function.

Logically AND’ed with register 16, bit 8.

Read/Write

Configuration: Config1

Configuration bits (see Table 3−10), default value = 0

When CONFIG1 = low, this bit can be set to 1.

When CONFIG1 = high, this bit is read-only.

Logically ORed with register 16, bit 7.

Read/Write

Configuration: Config0

Configuration bits (see Table 3−10), default value = 0

When CONFIG0 = low, this bit can be set to 1.

When CONFIG0 = high, this bit is read-only.

Logically ORed with register 16, bit 6.

Read/Write

Preemphasis: Pre2

Programmable preemphasis control (see Table 3−9), default value = 0.

Logically ORed with register 16, bit 5.

Read/Write

Preemphasis: Pre1

Programmable preemphasis control (see Table 3−9), default value = 0.

Logically ORed with register 16, bit 4.

Read/Write

Loopback

1 = Enable loopback mode on channel D.

0 = Disable loopback mode on channel D (default).

Logically ORed with register 0, bit 14

Read/Write

PRBS enable

1 = Enable PRBS internal generation and verification on channel D

0 = Normal operation (default)

Logically ORed with register 16, bit 2

When PRBSEN = low, this bit can be set to 1.

When PRBSEN = high, this bit is read-only.

Read/Write

Comma detect enable

1 = Enable K28.5 code detection and bit alignment on channel D (default).

0 = Disable K28.5 code detection on channel D.

Logically AND’ed with SYNCEN and register 16, bit 1

Read/Write

Power down

1 = Power-down mode is enabled for channel D.

0 = Normal operation (default)

Logically ORed with register 0, bit 11

Read/Write

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