TLK3114SCZPV datasheet(7/68 Pages) TI1

7 / 68 page

1−1

1 Description

The TLK3114SC device is a flexible quad serial transceiver, delivering high-speed, bidirectional, point-to-point data

transmissions to provide up to 10 Gbps of data transmission capacity. The TLK3114SC device is terminal compatible

with the TLK3104SA quad serial transceiver and supports an operating range of serial data rates from 2.5 Gbps to

3.125 Gbps. The primary application of this device is to provide building blocks for developing point-to-point

baseband data transmission over controlled-impedance media of approximately 50

Ω. The transmission media can

be printed-circuit board (PCB) traces, copper cables, or fiber-optical media. The ultimate rate and distance of data

transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.

The TLK3114SC device performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions

for a physical layer interface. The TLK3114SC device also provides a selectable 8-b/10-b encode/decode function.

The serial transmitter is implemented using differential pseudoemitter controlled logic (PECL) compatible signaling

called voltage mode logic (VML) that eliminates the need for external components. The serial receiver employs an

equalization circuit to maximize receive capabilities.

The four transceivers in the TLK3114SC device can be configured as either four separate links or synchronized

together as a single data path. The TLK3114SC device supports both the 32-bit data path, 4-bit control, 10-gigabit

media independent interface (XGMII), and the extended auxiliary unit interface (XAUI) specified in the IEEE 802.3ae

10-Gigabit Ethernet standard. Figure 1−1 shows an example system block diagram for the TLK3114SC device used

as an XGMII extended sublayer (XGXS) device to provide an additional trace distance on PCB for data being

transferred between the switching fabric and optical transceiver modules.

MAC/

Switch

Fabric

20”

6”

XAUI

6”

3”

Management

XGXS

TLK3114SC

MDIO

MDC

XGXS

TLK3114SC

MDIO

MDC

PCS

MDIO MDC

TX+

TX−

RX+

RX−

TDA..D[9:0]

TCA..D

RCA..D

RDA..D[9:0]

TDA..D[9:0]

RDA..D[9:0]

TCA..D

RCA..D

16:1

TX MUX

Clk

E/O

1:16

CDR/

Clk

O/E

De-MUX

XGMII

Figure 1−1. System Block Diagram (Chip-to-Chip Implementation)

Figure 1−2 shows an example system block diagram for TLK3114SC device used to provide the 10-Gbps Ethernet

physical coding sublayer (as defined in IEEE802.3ae Clause 48) to coarse wavelength division multiplexed optical

transceiver.

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