PIC16F1516 datasheet(339/344 Pages) MICROCHIP

339 / 344 page

 2011 Microchip Technology Inc.

Preliminary

DS41452B-page 339

PIC16(L)F1516/7/8/9

Reset................................................................................... 67

Reset Instruction ................................................................. 70

Resets................................................................................. 67

Associated Registers .................................................. 74

Revision History ................................................................ 333

Software Simulator (MPLAB SIM)..................................... 315

SPBRG Register ................................................................. 35

SPBRGH Register ............................................................ 249

SPBRGL Register ............................................................. 249

Special Event Trigger........................................................ 145

Special Function Registers (SFRs)..................................... 34

SPI Mode (MSSP)

Associated Registers ................................................ 195

SPI Clock .................................................................. 191

SSPADD Register....................................................... 36, 236

SSPBUF Register ............................................................... 36

SSPCON Register .............................................................. 36

SSPCON1 Register .......................................................... 233

SSPCON2 Register .......................................................... 234

SSPCON3 Register .......................................................... 235

SSPMSK Register............................................................. 236

SSPOV.............................................................................. 222

SSPOV Status Flag .......................................................... 222

SSPSTAT Register ..................................................... 36, 232

R/W Bit...................................................................... 201

Stack ................................................................................... 39

Accessing.................................................................... 39

Reset........................................................................... 41

Stack Overflow/Underflow................................................... 70

STATUS Register ............................................................... 25

SUBWFB........................................................................... 281

T1CON Register ......................................................... 34, 167

T1GCON Register............................................................. 168

T2CON (Timer2) Register ................................................. 173

T2CON Register ................................................................. 34

Temperature Indicator Module.......................................... 139

Thermal Considerations.................................................... 294

Timer0............................................................................... 155

Associated Registers ................................................ 157

Operation .................................................................. 155

Specifications............................................................ 301

Timer1............................................................................... 159

Associated registers.................................................. 169

Asynchronous Counter Mode ................................... 161

Reading and Writing ......................................... 161

Clock Source Selection............................................. 160

Interrupt..................................................................... 163

Operation .................................................................. 160

Operation During Sleep ............................................ 163

Prescaler................................................................... 161

Secondary Oscillator................................................. 161

Specifications............................................................ 301

Timer1 Gate

Selecting Source............................................... 161

TMR1H Register ....................................................... 159

TMR1L Register........................................................ 159

Timer2............................................................................... 171

Associated registers.................................................. 174

Timer2/4/6

Associated registers.................................................. 174

Timers

Timer1

T1CON ............................................................. 167

T1GCON........................................................... 168

Timer2

T2CON ............................................................. 173

Timing Diagrams

A/D Conversion ........................................................ 303

A/D Conversion (Sleep Mode).................................. 304

Acknowledge Sequence ........................................... 224

Asynchronous Reception.......................................... 244

Asynchronous Transmission .................................... 240

Asynchronous Transmission (Back to Back) ............ 241

Auto Wake-up Bit (WUE) During Normal Operation. 256

Auto Wake-up Bit (WUE) During Sleep .................... 256

Automatic Baud Rate Calibration ............................. 254

Baud Rate Generator with Clock Arbitration............. 217

BRG Reset Due to SDA Arbitration During Start

Condition .......................................................... 227

Brown-out Reset (BOR)............................................ 299

Brown-out Reset Situations ........................................ 69

Bus Collision During a Repeated Start Condition

(Case 1)............................................................ 228

Bus Collision During a Repeated Start Condition

(Case 2)............................................................ 228

Bus Collision During a Start Condition (SCL = 0) ..... 227

Bus Collision During a Stop Condition (Case 1)....... 229

Bus Collision During a Stop Condition (Case 2)....... 229

Bus Collision During Start Condition (SDA only) ...... 226

Bus Collision for Transmit and Acknowledge ........... 225

Capture/Compare/PWM (CCP) ................................ 302

CLKOUT and I/O ...................................................... 297

Clock Synchronization .............................................. 214

Clock Timing............................................................. 296

Fail-Safe Clock Monitor (FSCM)................................. 63

First Start Bit Timing ................................................. 218

I2C Bus Data............................................................. 309

I2C Bus Start/Stop Bits ............................................. 308

I2C Master Mode (7 or 10-Bit Transmission) ............ 221

I2C Master Mode (7-Bit Reception) .......................... 223

I2C Stop Condition Receive or Transmit Mode......... 224

INT Pin Interrupt ......................................................... 78

Internal Oscillator Switch Timing ................................ 58

Repeat Start Condition ............................................. 219

Reset Start-up Sequence ........................................... 71

Reset, WDT, OST and Power-up Timer ................... 298

Send Break Character Sequence............................. 257

SPI Master Mode (CKE = 1, SMP = 1) ..................... 306

SPI Mode (Master Mode) ......................................... 191

SPI Slave Mode (CKE = 0) ....................................... 307

SPI Slave Mode (CKE = 1) ....................................... 307

Synchronous Reception (Master Mode, SREN) ....... 261

Synchronous Transmission ...................................... 259

Synchronous Transmission (Through TXEN)........... 259

Timer0 and Timer1 External Clock ........................... 301

Timer1 Incrementing Edge ....................................... 163

Two Speed Start-up.................................................... 61

USART Synchronous Receive (Master/Slave) ......... 305

USART Synchronous Transmission (Master/Slave). 304

Wake-up from Interrupt............................................... 88

Timing Parameter Symbology .......................................... 295

Timing Requirements

I2C Bus Data............................................................. 310

SPI Mode.................................................................. 308

TMR0 Register.................................................................... 34

TMR1H Register ................................................................. 34

TMR1L Register.................................................................. 34

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