PIC16F1516 datasheet(336/344 Pages) MICROCHIP

336 / 344 page

PIC16(L)F1516/7/8/9

DS41452B-page 336

Preliminary

 2011 Microchip Technology Inc.

LP........................................................................ 53

OST..................................................................... 54

RC....................................................................... 55

XT ....................................................................... 53

Internal Modes ............................................................ 56

HFINTOSC.......................................................... 56

Internal Oscillator Clock Switch Timing............... 57

LFINTOSC .......................................................... 56

Clock Switching................................................................... 59

Code Examples

A/D Conversion......................................................... 146

Changing Between Capture Prescalers .................... 176

Initializing PORTA..................................................... 113

Writing to Flash Program Memory ............................ 106

Comparators

C2OUT as T1 Gate ................................................... 161

Compare Module. See Capture/Compare/PWM (CCP)

CONFIG1 Register.............................................................. 46

CONFIG2 Register.............................................................. 48

Core Function Register ....................................................... 33

Customer Change Notification Service ............................. 341

Customer Notification Service........................................... 341

Customer Support ............................................................. 341

Data Memory....................................................................... 24

DC and AC Characteristics ............................................... 311

DC Characteristics

Extended and Industrial ............................................ 292

Industrial and Extended ............................................ 285

Development Support ....................................................... 313

Device Configuration........................................................... 45

Code Protection .......................................................... 49

Configuration Word ..................................................... 45

User ID .................................................................. 49, 50

Device ID Register .............................................................. 50

Device Overview ........................................................... 13, 93

EEDATL Register.............................................................. 110

Effects of Reset

PWM mode ............................................................... 183

Electrical Specifications .................................................... 283

Enhanced Mid-range CPU .................................................. 19

Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART)............................... 237

Errata .................................................................................. 11

EUSART............................................................................ 237

Associated Registers

Baud Rate Generator........................................ 250

Asynchronous Mode ................................................. 239

12-bit Break Transmit and Receive................... 257

Associated Registers

Receive..................................................... 245

Transmit .................................................... 241

Auto-Wake-up on Break.................................... 255

Baud Rate Generator (BRG)............................. 249

Clock Accuracy ................................................. 246

Receiver............................................................ 242

Setting up 9-bit Mode with Address Detect....... 244

Transmitter........................................................ 239

Baud Rate Generator (BRG)

Auto Baud Rate Detect ..................................... 254

Baud Rate Error, Calculating ............................ 249

Baud Rates, Asynchronous Modes................... 251

Formulas ........................................................... 250

High Baud Rate Select (BRGH Bit) .................. 249

Synchronous Master Mode............................... 258, 262

Associated Registers

Receive .................................................... 261

Transmit.................................................... 259

Reception ......................................................... 260

Transmission .................................................... 258

Synchronous Slave Mode

Associated Registers

Receive .................................................... 263

Transmit.................................................... 262

Reception ......................................................... 263

Transmission .................................................... 262

Extended Instruction Set

ADDFSR................................................................... 273

Fail-Safe Clock Monitor ...................................................... 62

Fail-Safe Condition Clearing....................................... 62

Fail-Safe Detection ..................................................... 62

Fail-Safe Operation..................................................... 62

Reset or Wake-up from Sleep .................................... 62

Firmware Instructions ....................................................... 269

Fixed Voltage Reference (FVR)........................................ 137

Associated Registers ................................................ 138

Flash Program Memory ...................................................... 97

Associated Registers ................................................ 112

Configuration Word w/ Flash Program Memory........ 112

Erasing ..................................................................... 101

Modifying .................................................................. 107

Write Verify ............................................................... 109

Writing ...................................................................... 103

FSR Register ...................................................................... 33

FVRCON (Fixed Voltage Reference Control) Register..... 138

I2C Mode (MSSP)

Acknowledge Sequence Timing ............................... 224

Bus Collision

During a Repeated Start Condition................... 228

During a Stop Condition ................................... 229

Effects of a Reset ..................................................... 225

I2C Clock Rate w/BRG.............................................. 231

Master Mode

Operation.......................................................... 216

Reception ......................................................... 222

Start Condition Timing .............................. 218, 219

Transmission .................................................... 220

Multi-Master Communication, Bus Collision and

Arbitration ......................................................... 225

Multi-Master Mode .................................................... 225

Read/Write Bit Information (R/W Bit)........................ 201

Slave Mode

Transmission .................................................... 206

Sleep Operation........................................................ 225

Stop Condition Timing .............................................. 224

INDF Register ..................................................................... 33

Indirect Addressing ............................................................. 41

Instruction Format............................................................. 270

Instruction Set................................................................... 269

ADDLW..................................................................... 273

ADDWF..................................................................... 273

ADDWFC .................................................................. 273

ANDLW..................................................................... 273

ANDWF..................................................................... 273

BRA .......................................................................... 274

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