PIC16F1516 datasheet(247/344 Pages) MICROCHIP

247 / 344 page

 2011 Microchip Technology Inc.

Preliminary

DS41452B-page 247

PIC16(L)F1516/7/8/9

RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)

R/W-0/0

R-0/0

R-x/x

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

SPEN:

Serial Port Enable bit

= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

= Serial port disabled (held in Reset)

bit 6

RX9:

9-bit Receive Enable bit

= Selects 9-bit reception

= Selects 8-bit reception

bit 5

SREN:

Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

= Enables single receive

= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4

CREN:

Continuous Receive Enable bit

Asynchronous mode:

= Enables receiver

= Disables receiver

Synchronous mode:

= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

= Disables continuous receive

bit 3

ADDEN:

Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2

FERR:

Framing Error bit

= Framing error (can be updated by reading RCREG register and receive next valid byte)

= No framing error

bit 1

OERR:

Overrun Error bit

= Overrun error (can be cleared by clearing bit CREN)

= No overrun error

bit 0

RX9D:

Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

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