PIC16F1516 datasheet(231/344 Pages) MICROCHIP

231 / 344 page

 2011 Microchip Technology Inc.

Preliminary

DS41452B-page 231

PIC16(L)F1516/7/8/9

21.7

BAUD RATE GENERATOR

The MSSP module has a Baud Rate Generator avail-

able for clock generation in both I2C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSPADD register (Register 21-6).

When a write occurs to SSPBUF, the Baud Rate Gen-

erator will automatically begin counting down.

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

An internal signal “Reload” in Figure 21-39 triggers the

value from SSPADD to be loaded into the BRG counter.

This occurs twice for each oscillation of the module

clock line. The logic dictating when the reload signal is

asserted depends on the mode the MSSP is being

operated in.

Table 21-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

EQUATION 21-1:

FIGURE 21-40:

BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 21-4:

MSSP CLOCK RATE W/BRG

FCLOCK

FOSC

SSPADD

 4



----------------------------------------------

Note:

Values of 0x00, 0x01 and 0x02 are not valid

for SSPADD when used as a Baud Rate

Generator for I2C. This is an implementation

limitation.

FOSC

FCY

BRG Value

FCLOCK

(2 Rollovers of BRG)

16 MHz

4 MHz

09h

400 kHz(1)

16 MHz

4 MHz

0Ch

308 kHz

16 MHz

4 MHz

27h

100 kHz

4 MHz

1 MHz

09h

100 kHz

Note 1:

The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

SSPM<3:0>

BRG Down Counter

SSPCLK

FOSC/2

SSPADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

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