C5NPD0-DS datasheet(16/100 Pages) FREESCALE

16 / 100 page

C5NP

August 8, 2000

Operating temperatiure range added.

Power sequencing diagram updated.

BMU timing diagram updated.

TLU timing diagram updated.

QMU timing diagram updated.

March 26, 2001

Chapter 1 contains the following revisions:

• Fabric Processor Interface Frequency changed from 100

MHz to 110 MHz thruoughout.

• TLU interface memory was incorrectly noted at 64 MBytes.

Changed to 32 MBytes.

The maximum amount of memory supported by the TLU is

32MBytes in four banks.

Chapter 2 contains the following revisions:

• Buffer Management Unit (BMU) has 161 pins

• Added Figure 5. PROM Interface Timing Outline

• Added Figure 7. Observe-Only Cell

• Added Figure 8. Cell Design That Can Be Used for Both

Input and Output Pins

• PROM Interface Timing Outline added.

• Numerous changes in tables 17, 18 and 19

• Data lines incorrectly noted at 128. The useful

configuration is 139 data lines and all 12 address lines.

• The TLU SRAM interface was incorrectly noted at 64

MBytes. Changed to 32 MBytes.

Chapter 3 contains the following revisions:

• Table 40, Gigabit Ethernet (TBI) Timing Description, Tcgr

min value of -1.0 removed.

• Figure 16, OC 12 Clock Duty Cycle was added

• Tc12d added to Table 42

• Figure 17, Executive Processor PCI Timing Diagram PGNTX

is only an input. PGNTX Output removed.

• Tpgo, Tpgz, Tpgv removed from Table 43.

Chapter 4 contains the following revisions:

• Mechanical specs changed.

Thru-out

39, 40

Table 2 C-5 Network Processor Data Sheet Revision History

REVISION DATE

CHANGE

PAGE NO.

Freescale Semiconductor, Inc.

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