C5NPD0-DS datasheet(22/100 Pages) FREESCALE

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CHAPTER 1: FUNCTIONAL DESCRIPTION

C5NP

Channel Processors

The C-5 NP contains sixteen programmable Channel Processors (CPs) that receive,

process, and transmit network data. The number of CPs per port is configurable,

depending on the line interface. Typically one CP is assigned to each port for medium

bandwidth applications (Fast Ethernet to OC-3). Multiple CPs can be assigned to a port in

a configuration called channel aggregation in high bandwidth applications (greater than

OC-3). Multiple logical ports can be assigned to a single CP, with the addition of an

external multiplexor, for low bandwidth applications, such as DS1 to DS3.

The C-5 NP’s architecture supports a variety of industry-standard serial and parallel

protocols and individual port data rates including:

• 10Mb Ethernet (RMII)

• 100Mb Ethernet (RMII)

• 1Gb Ethernet (GMII and TBI)

• OC-3

• OC-12

• DS1/DS3, supported through the use of external framers/multiplexors

The C-5 NP’s programmability can also support a variety of special interfaces, such as

various xDSL encapsulations and proprietary protocols.

Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet

processing and a set of microprogrammable, special-purpose processors, called Serial

Data Processors (SDPs), that provide features such as Ethernet MAC and SONET framing,

multichannel HDLC, and ATM cell delineation. This means you usually only need to

include PHYs to complete the system.

Executive Processor

The Executive Processor (XP) serves as a centralized computing resource for the C-5 NP

and manages the system interfaces.

The XP performs conventional supervisory tasks in the C-5 NP, including:

• Reset and initialization of the C-5 NP

• Program loading and control of CPs

• Centralized exception handling

Freescale Semiconductor, Inc.

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