C5NPD0-DS datasheet(50/100 Pages) FREESCALE

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CHAPTER 2: SIGNAL DESCRIPTIONS

C5NP

QMU SRAM Interface

Signals

The QMU signals are described in Table 26. The QMU’s clock frequency is 1/

2 the internal

core clock frequency.

Power Supply Signals

Power supply and ground signals are described in Table 27 and their pinouts are shown in

Figure 6.

Table 26 QMU SRAM Interface Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O*

SIGNAL DESCRIPTION

QCPAR

A10

Not used

QCLK

G12

LVTTL

Clock Signal to the memory ICs

QCMD0 - QCMD15

B10, C10, D10, E10, F10, B11, D11, F11,

A12, B12, C12, D12, E12, B13, D13, F13

LVTTL

Memory Address [15: 0] to the memory

ICs

QDPAR

LVTTL

I/O

Data parity

QDATA0 - QDATA31

D1, F1, F2, B2, C2, D2, E2, B3, D3, F3, A4,

B4, C4, D4, E4, F4, B5, D5, F5, A6, B6, C6,

D6, E6, F6, B7, D7, F7, C8, D8, E8, F8

LVTTL

I/O

Memory Data

QSFLOW

LVTTL

Not Used

QXCTRL0

LVTTL

Rd/Wr (Read is true high, write is true low)

QXCTRL1

LVTTL

Memory Address [16] to the memory ICs

QXRQST

Reserved

Note: Requires Pullup or Pulldown.

TOTAL PINS

* During normal (non-scan) operation.

Table 27 Power Supply Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

SIGNAL DESCRIPTION

VDD

A3, A11, A15, A23, A27, C1, C5, C13, C17, C25, C29,

E3, E7, E15, E19, E27, G5, G9, G17, G21, G29, I7, I11,

I19, I23, J12, K1, K9, K13, K21, K25, L14, M3, M11,

M15, M23, M27, O1, O5, O13, O17, O25, O29, Q3, Q7,

Q15, Q19, Q27, S5, S9, S17, S21, S29, U7, U11, U19,

U23, W1, W9, W13, W21, W25, Y3, Y11, Y15, Y23, Y27,

AA1, AA5, AA13, AA17, AA25, AA29, AC3, AC7, AC15,

AC19, AC27

Core Supply Voltage (1.8V Input)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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