C5NPD0-DS datasheet(24/100 Pages) FREESCALE

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CHAPTER 1: FUNCTIONAL DESCRIPTION

C5NP

or cells from the C-5 NP to a hardware interface that provides connectivity to other

network processors or other similar line processing hardware. There are numerous

parameters that can be configured within the FP to allow the interface to be adapted to

different fabric protocols. The FP is Utopia-1, 2 and Utopia-3, IBM PRIZMA, and PowerX

(Csix-L0) compatible.

The FP can be configured to run at any frequency up to 110MHz, and the receive and

transmit data buses are 16 or 32 bits wide. This allows a wide range of supported

bandwidths to and from the switching fabric, all the way up to 3200Mbps full duplex

bandwidth.

Buffer Management Unit

The Buffer Management Unit (BMU) interfaces the C-5 NP to external pipeline

architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned

and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It

is also used as second level storage in the XP memory hierarchy.

The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two

internal control bits, and nine SECDED (single error correction-double error detection) ECC

(error correction code) bits. The interface is compliant with the PC100 standard and

operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh

period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the

C-5 Network Processor Architecture Guide for more details).

The C-5 NP uses auto-refresh mode and the interface, (which is not configurable),

transfers four bits of data for each read and write using a sequential burst type.

Some of these parameters are programmed into the SDRAMs’ mode register and can be

applied only once per power cycle. The ECC functionality can be enabled or disabled via

configuration register writes.

If needed, the interface can narrowed to 128bits by disabling ECC and providing board

pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the

board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU

supports SDRAM devices that use 12 address lines. Internal address calculation paths limit

the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.

Table Lookup Unit

The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used

for statistics accumulation and retrieval and as general data storage. The TLU

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