C5NPD0-DS datasheet(38/100 Pages) FREESCALE

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CHAPTER 2: SIGNAL DESCRIPTIONS

C5NP

Table 13 OC-12 Signals Example

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 6

LVTTL

TCLK

Deskewed Transmit Clock (77.76MHz). This clock is used to

synchronize the transmit data.

CPn_1

Table 6

LVTTL

TCLK1

Transceiver Transmit Clock. This clock sets the frequency of the

transmit data and is typically sourced by the PHY chip.

CPn_2

Table 6

LVTTL

TXD(0)

Transmit Data (byte-wide data, least significant bit)

CPn_3

Table 6

LVTTL

TXD(1)

Transmit Data

CPn_4

Table 6

LVTTL

TXD(2)

Transmit Data

CPn_5

Table 6

LVTTL

TXD(3)

Transmit Data

CPn_6

Table 6

LVTTL

00F

Out of Frame

CPn+1_0

Table 6

CPn+1_1

Table 6

CPn+1_2

Table 6

LVTTL

TXD(4)

Transmit Data

CPn+1_3

Table 6

LVTTL

TXD(5)

Transmit Data

CPn+1_4

Table 6

LVTTL

TXD(6)

Transmit Data

CPn+1_5

Table 6

LVTTL

TXD(7)

Transmit Data (byte-wide data, most significant bit)

CPn+1_6

Table 6

CPn+2_0

Table 6

CPn+2_1

Table 6

LVTTL

RCLK

Receive Clock (77.76MHz)

CPn+2_2

Table 6

LVTTL

RXD(0)

Receive Data (byte-wide receive data, least significant bit)

CPn+2_3

Table 6

LVTTL

RXD(1)

Receive Data

CPn+2_4

Table 6

LVTTL

RXD(2)

Receive Data

CPn+2_5

Table 6

LVTTL

RXD(3)

Receive Data

CPn+2_6

Table 6

LVTTL

Frame Synchronization Pulse. This is valid during the third A2 of

the receive SONET frame.

CPn+3_0

Table 6

CPn+3_1

Table 6

CPn+3_2

Table 6

LVTTL

RXD(4)

Receive Data

CPn+3_3

Table 6

LVTTL

RXD(5)

Receive Data

CPn+3_4

Table 6

LVTTL

RXD(6)

Receive Data

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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