C5NPD0-DS datasheet(53/100 Pages) FREESCALE

53 / 100 page

Signals Grouped by Pin Number

V 04

During JTAG, SCLK and SCLKX must remain as differential inputs.

No Connection Pins

No connection pins are listed in Table 29.

Signals Grouped by Pin

Number

The C-5 NP signals are listed by pin number in Table 30.

Table 28 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines

SIGNAL NAME

PIN #

TOTAL

TYPE

SIGNAL DESCRIPTION

JTCK

T11

LVTTL

Test Clock

JTMS*

Z15

LVTTL

Test Mode Select. High selects modes

as defined in the IEEE 1149.1 JTAG

specification.

JTRSTX†

X15

LVTTL

Test Reset (low active)

JTDI†

AB15

LVTTL

Test Data In

JTDO

V15

LVTTL

Test Data Out

JHIGHZ

T12

LVTTL

Turns off all output drivers when High

JCLKBYP

T13

LVTTL

1X or 2X Clock Mode Select. Low

selects 1X, High selects 2X.

JSE

S12

LVTTL

Scan Enable. High enables scan test.

JS00-JS09

L12, N13, N12, P13, P12, Q12, R13, R12,

R11, R10

LVTTL

Scan Out Pins

TOTAL PINS

* According to the IEEE 1149.1 specification, the JTMS, JTRST, and JTDI pins must have internal pullups. While the C-5 NP does not currently have pads

with pullups, customers can pull up these three pins on the board.

Table 29 No Connection Pins

SIGNAL NAME

PIN #

TOTAL

TYPE

SIGNAL DESCRIPTION

NC1 - NC11

I18, H17, H18, N10, P10, N11, P11, U14,

V14, U16, V16

Reserved for future functionality

TOTAL PINS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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