PCF2127ATSLASH1 datasheet(57/80 Pages) NXP

57 / 80 page

PCF2127A_2

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Product data sheet

Rev. 02 — 7 May 2010

57 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

9.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines are

connected to a positive supply via a pull-up resistor. Data transfer is initiated only when

the bus is not busy.

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line remains

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as control signals (see Figure 38).

9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition S. A

LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOP

condition P (see Figure 39).

Remark: For the PCF2127A a repeated START is not allowed. Therefore a STOP has to

be released before the next START.

9.2.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves.

The PCF2127A can act as a slave transmitter and a slave receiver.

Fig 38. Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 39. Definition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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