PCF2127ATSLASH1 datasheet(49/80 Pages) NXP

49 / 80 page

PCF2127A_2

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Product data sheet

Rev. 02 — 7 May 2010

49 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

8.13.4 Watchdog timer interrupts

The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0]

bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which

follows the status of the watchdog timer flag WDTF (register Control_2). No pulse

generation is possible for watchdog timer interrupts.

The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot

be cleared by using the interface. Instructions for clearing it can be found in

Section 8.11.6.

8.13.5 Alarm interrupts

Generation of interrupts from the alarm function is controlled via the bit AIE (register

Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register

Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for

alarm interrupts.

(1) Indicates normal duration of INT pulse.

The timing shown for clearing CDTF is also valid for the non-pulsed interrupt mode, i.e. when

TI_TP is logic 0, where the INT pulse may be shortened by setting CDTIE logic 0.

Fig 29. Example of shortening the INT pulse by clearing the CDTF flag

001aaf909

countdown counter

CDTF

INT

SCL

instruction

CLEAR INSTRUCTION

8th clock

(1)

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 30. AF timing diagram

001aaf910

minute counter

minute alarm

INT

SCL

instruction

CLEAR INSTRUCTION

8th clock

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